Clock signals are used to control the timing of circuits and for example control when signals are to be applied and when certain operations are to commence. one example of a known arrangement which uses clock signals is shown in FIG. 1. A synchronous dynamic random access memory SDRAM 2 receives three inputs 4, 6 and 8 from an interface 10. The first input 4 provides a clock signal, the second input 6 provides data to be written into the SDRAM 2 whilst the third input 8 provides the address at which the data is to be written. The clock signal input to the SDRAM 2 from the first input 4 controls the timing of the operation of the SDRAM 2 such as the opening and closing of pages of the SDRAM 2 and the writing of the data into the required locations.
The clock signal input to the SDRAM 2 is generated from the internal clock .phi. of the interface 10. The internal clock .phi. passes through elements which introduce varying amounts of delay. These elements are represented by delay 14. In practice the amount of delay provided by the delay elements varies over time, for example due to changes in temperature. The interface 10 uses the internal clock .phi. to control the timing of the data and address signals. In order to ensure that the SDRAM 2 operates correctly, it should be ensured that the internal clock .phi. signal is in phase with the clock signal output by the interface 10. Generally, problems are avoided if the internal clock .phi. is in phase with the output clock even if the output clock is delayed with respect to the internal clock .phi.. A number of solutions have been proposed to ensure that the internal clock .phi. and the output clock are in phase.
In one solution, the internal clock .phi. is input to a variable delay 12, the output of which is connected to delay 14 which varies with time due to changes in temperature. The output of the delay 14 provides the clock output of the interface 10 which is input to the SDRAM 2. The internal clock .phi. is also input to a comparator 16 which also receives the output from the delay 14. The comparator 16 compares the phase of the internal clock .phi. with the phase of the signal output by the delay 14. The comparator 16 generates a control signal which is output to the variable delay 12 based on the results of the comparison. The control signal is arranged to cause the delay provided by the variable delay 12 to be such that the phase difference between the compared signals is n.times.360.degree. where n is an integer.
The variable delay 12 can take the form shown in FIG. 2. The variable delay 12 shown in FIG. 2 provides a single delay path with a series of outputs 20 along its length. Each of the outputs 20 provide a different delay with those outputs 20 which are closest to the input providing the shortest delays and those outputs closest to the output of the variable delay 12 providing the longest delays. The delay provided by the variable delay 12 is varied by selecting the appropriate output. Consider the case where the delay provided by variable delay 12 is being reduced and the output nearest to the input of the variable delay provides the current output with a delay of x.degree.. In order to effectively reduce the phase by y.degree. it is necessary to go to the output which provides a delay of 360+(x-y).degree.. In order to ensure that this transition is available, it is necessary to ensure that the delay values of x and (x-y)+360.degree. are both available at the same time and that the delay can be adjusted as required. These two requirements results in the need for two control loops one for defining the active part of the path and one loop to select the required delay from the active path. The active part of the delay path is that part of the path from which the delay outputs are taken. Transitions can thus be made from one part of the path to another as described hereinbefore. Typically, the path is regulated to ensure that its length is one clock cycle and that the required delay is selected from an appropriate point along it.
The provision of a multi output variable delay is disadvantageous in that the delay itself as well as the regulation mechanism can be costly in terms of silicon area. Additionally the regulation mechanism is an analogue structure which can be complex to design.
As an alternative to the regulation of the path, the variable delay can be constructed to be much longer than one clock cycle so that sufficient delay and resolution are always available. However, this solution also requires a large silicon area.
Variable delay paths with single outputs are known but also suffer from the problems relating to transitions from a delay of a.degree. to a delay of a+360.degree..
Another solution which has been proposed to deal with the alteration in the phase of the clock signal output by the interface 10 as compared to the internal clock signal .phi. is to use a phase locked loop. However, this solution is disadvantageous in that phase locked loops are not particularly robust and are complex. Accordingly it is preferred to avoid the use of phase locked loops in at least some applications.